Cacao is a compact 12-channel audio-frequency signal-acquisition board built around the RP2350. It explores how modern, accessible components can consolidate multi-channel acquisition, buffering, storage, and Ethernet communication onto a single 80 x 50 mm PCB.

Overview

Cacao was developed independently as a proof of concept alongside an industrial R&D internship. The project acts as a technical calling card: a complete architecture, schematic, and dense PCB layout designed to demonstrate what can be achieved with a modern microcontroller and cost-effective audio-conversion hardware.

Twelve differential audio inputs are digitized by three TLV320ADC5140 ADCs at 44.1 kHz. The RP2350 collects and processes the resulting data before sending it over 100BASE-TX Ethernet through a W5500 or storing it locally on a microSD card.

Key Features

RP2350 in the 80-pin package with internal flash
12 differential audio-input channels
Three TLV320ADC5140 four-channel ADCs synchronized by a 2.5 ppm clock
44.1 kHz acquisition with planned 12- or 16-bit sample handling
W5500-based 100BASE-TX Ethernet output
8 MB external RAM for acquisition buffering
MicroSD storage for standalone data capture
USB-C 5 V power input
3.3 V buck supply for the digital electronics
Separate low-noise 3.3 V analog rail using an LP5907MFX-3.3/NOPB LDO
Four-layer, 80 x 50 mm PCB with more than 200 components
Components on both sides, with most passive components placed on the back

The Micro-USB connectors are used as compact keyed connectors for the differential analog channels and their 5 V amplifier supply. They are not USB data ports.

Engineering Focus

The principal layout challenge was integrating 12 analog channels, three synchronized ADCs, local buffering, storage, Ethernet, and the required power architecture within an 80 x 50 mm footprint. Particular attention was given to separating low-noise analog supplies from the general digital rail, maintaining clean reference and return paths, and placing a large number of passive components without increasing the board area.

An alternative future configuration could replace the W5500 and external RAM with a W6300 connected through QSPI, reducing the number of separate devices while retaining high-speed Ethernet communication.

The firmware will have to be as efficient as possible to allow 10-12 channels at the same time to be sampled and transferred to the W5500.

Project Status

V1.0 is currently being assembled by myself and testing will soon start.

known V1 issues

There are a few problems with the V1 of this PCB and they are pretty serious so I would advise not to send any of these files to be produced and to either modify these mistakes or to wait for a V1.1 or V2 of this board.

Bad selection of Rp2350 ports

This is the most embarassing problem of them all. I put a bit too much faith in the MUX capabilities of the rp MCU and choose the SPI and QSPI pins incorrectly.

The RAM needs to be totally rerouted, 5/6 pins are wrong and need to be changed :

RAM_QSD3 not to GPIO 16 but to QSPI_SD3
RAM_QSD2 not to GPIO 17 but to QSPI_SD2
RAM_QSD1 not to GPIO 18 but to QSPI_SD1
RAM_QSD0 not to GPIO 19 but to QSPI_SD0
RAM_QSCLK not to GPIO 20 but to QSPI_SCLK

This is extremely embarassing as the pins are even labeled, I should have seen this before sending the files to production.

The W5500 and SD CARD are wired wrong too as even if the selected pins are correct, not all pins of a SPI bank can do every job.

So you have to do these swaps :

ETH_CS GPIO28 to GPIO29
ETH_SCLK GPIO29 to GPIO30
ETH_MISO GPIO30 to GPIO28

And for the SD card its all wrong as I did not plan for SPI0 and SPI1 differences.

I would advise not to botch anything but rather use a PIO SPI that then can be used on pretty much any pins.

Those mistakes are extremely embarassing but they exist and will have to be dealt with when assembling the boards.