Update after testing

2026-08-16 02:51:29 +02:00
parent 51d6ae0c19
commit afad9e813c
13 changed files with 123404 additions and 5677 deletions
@@ -15,6 +15,7 @@
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@@ -3,6 +3,8 @@
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@@ -48,7 +50,23 @@
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@@ -77,6 +95,7 @@
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@@ -94,6 +113,7 @@
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@@ -113,9 +133,12 @@
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@@ -463,6 +500,7 @@
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@@ -523,6 +562,10 @@
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@@ -842,12 +888,21 @@
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-      "Root"
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@@ -870,5 +925,11 @@
      "Memory"
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@@ -6,23 +6,26 @@ Cacao is a compact 12-channel audio-frequency signal-acquisition board built aro
 ![Cacao PCB - 3D render](figures/Recto.png)
 ![Cacao PCB - 3D render](figures/Verso.png)
-(On the real pic you can see pretty obvious shorts on different chips, the board was just out of the oven and the shorts were dealt with before first bring up)
+The assembled board shown above had just come out of the reflow oven. Some visible solder bridges were cleaned up before the first bring-up.
 ## Overview
-Cacao was developed independently as a proof of concept alongside an industrial R&D internship. The project acts as a technical calling card: a complete architecture, schematic, and dense PCB layout designed to demonstrate what can be achieved with a modern microcontroller and cost-effective audio-conversion hardware.
+Cacao was developed independently as a proof of concept alongside an industrial R&D internship. The project acts as a technical calling card: a complete architecture, schematic, firmware stack, and dense PCB layout intended to demonstrate what can be achieved with a modern microcontroller and cost-effective audio-conversion hardware.
-Twelve differential audio inputs are digitized by three TLV320ADC5140 ADCs at 44.1 kHz. The RP2350 collects and processes the resulting data before sending it over 100BASE-TX Ethernet through a W5500 or storing it locally on a microSD card.
+Twelve differential audio inputs are digitized by three TLV320ADC5140 ADCs synchronized to the same clock. The RP2350 acquires the resulting streams and can transmit them over a local network through a W5500 100BASE-TX Ethernet controller.
 The current firmware has successfully demonstrated continuous simultaneous acquisition of all 12 channels at 44.1 kHz with 16-bit samples, streamed over Ethernet without requiring intermediate RAM buffering.
 ## Key Features
 - RP2350 in the 80-pin package with internal flash
 - 12 differential audio-input channels
 - Three TLV320ADC5140 four-channel ADCs synchronized by a 2.5 ppm clock
- 44.1 kHz acquisition with planned 12- or 16-bit sample handling
+- Simultaneous 12-channel acquisition at 44.1 kHz / 16 bits per sample
 - W5500-based 100BASE-TX Ethernet output
- 8 MB external RAM for acquisition buffering
+- Continuous network streaming of all 12 channels
- MicroSD storage for standalone data capture
+- 8 MB external RAM provisioned for acquisition buffering
 - MicroSD storage interface for standalone data capture
 - USB-C 5 V power input
 - 3.3 V buck supply for the digital electronics
 - Separate low-noise 3.3 V analog rail using an LP5907MFX-3.3/NOPB LDO
@@ -33,102 +36,152 @@ The Micro-USB connectors are used as compact keyed connectors for the differenti
 ## Engineering Focus
-The principal layout challenge was integrating 12 analog channels, three synchronized ADCs, local buffering, storage, Ethernet, and the required power architecture within an 80 x 50 mm footprint. Particular attention was given to separating low-noise analog supplies from the general digital rail, maintaining clean reference and return paths, and placing a large number of passive components without increasing the board area.
+The principal layout challenge was integrating 12 analog channels, three synchronized ADCs, local buffering, storage, Ethernet, and the required power architecture within an 80 x 50 mm footprint.
-An alternative future configuration could replace the W5500 and external RAM with a W6300 connected through QSPI, reducing the number of separate devices while retaining high-speed Ethernet communication.
+Particular attention was given to separating the low-noise analog supplies from the general digital rail, maintaining clean reference and return paths, and fitting a large number of passive components without increasing the board area.
-The firmware will have to be as efficient as possible to allow 10-12 channels at the same time to be sampled and transferred to the W5500.
+The firmware also represents an important part of the project. The RP2350 has to receive multiple synchronized ADC data streams while simultaneously moving the acquired samples toward the Ethernet interface with minimal CPU and memory overhead.
 Because of a V1 SPI pin-assignment issue, the W5500 currently runs through an RP2350 PIO implementation rather than the native SPI peripheral. Despite the reduced SPI bandwidth, the system can continuously acquire and transmit all 12 channels at 44.1 kHz / 16 bits over the local network.
 This is not necessarily the absolute throughput limit of the architecture, but it is close to the useful range expected from the current PIO SPI implementation. A future revision will move the Ethernet interface to correctly assigned hardware SPI pins, providing additional bandwidth and reducing the amount of firmware required for the interface.
 An alternative future configuration could also replace the W5500 and external RAM with a W6300 connected through QSPI, reducing the number of separate devices while retaining high-speed Ethernet communication.
 ## Assembly
-V1's PCB's were manufactured by the company Aisler. It was a first test for me and I liked the service a lot.
+The V1 PCBs were manufactured by Aisler. This was my first time using their service and the manufacturing quality was very good.
-PCB's arrived naked and I assembled three prototypes by hand at school where we have small manually controlled "pick and places" machines that help speed up the process of compared to using tweazers to place components.
+The PCBs arrived unassembled and I assembled three prototypes at school. The school has small manually controlled pick-and-place machines, which significantly speed up component placement compared with assembling the entire board using tweezers.
 ![CACAO Board](figures/Bare_PCB.jpeg)
 ![CACAO Board](figures/Compare.png)
-On the top you can see the bare PCB and on the bottom you can see a fully assembled board next to the boards she is supposed to compete against. (The others are blurred as they are property of the company I worked in but they are the boards that are doing 12X less work as cacao does)
+The image above shows a bare Cacao PCB and a fully assembled board next to the existing acquisition hardware it was designed to compare against.
 The other boards are blurred because they are property of the company where I worked. The comparison is nevertheless useful for showing the amount of functionality Cacao integrates onto a single board.
 ## Project Status
-V1.0 has been received and assembled. It is currently in testing but I can already say that :
+V1.0 has been manufactured, assembled, and brought up successfully.
-+ All power buses are operational
+The main architecture is operational:
 + Ethernet works with PIO SPI instead of native SPI 
 + RP2350 can be flashed using the USB and SWD
 + All ADC's are working and be communicated with
 + After modifiying the micro USB connection data can be read from ADC's to the Rp2350 and then to USB or Ethernet
-So basically all the main features are working.
+- All power rails are working correctly
 - The RP2350 can be programmed through both USB and SWD
 - Ethernet communication through the W5500 is operational
 - The W5500 is currently driven using PIO SPI because of the V1 GPIO assignment
 - All three TLV320ADC5140 ADCs are operational and communicating correctly with the RP2350
 - All 12 analog channels are being sampled
 - All 12 channels have been acquired simultaneously at 44.1 kHz / 16 bits per sample
 - The complete 12-channel stream has been transmitted continuously over the local Ethernet network
 - The streaming test does not rely on the external RAM as an intermediate acquisition buffer
 - A corrected Micro-USB input has been tested with the intended external preamplifier and produces the expected signal level
-Here is what cannot be tested 
+The continuous Ethernet test indicates that the RP2350, ADC acquisition path, PIO SPI implementation, W5500, and network firmware can sustain the current target acquisition rate without accumulating an acquisition backlog.
-+ The RAM has not been installed as all of its wiring is wrong and a PIO implementation could work but not fast enough for my use case so it will need to wait for a new version
+### Not tested on V1
 + The SD card port was not received
-Here is what is still in testing 
+Two interfaces have not yet been functionally tested:
-+ Actual throughput limit through the W5500 with the reduced SPI bandwidth
+- External RAM
-+ Quantifying the signal integrity coming from the analog capture. (it is looking pretty good on my first tests)
+- MicroSD storage
-## known V1 issues
+Part of the BOM could not be delivered before assembly, so the required components were not available for the first prototype batch.
-The first version as always has problems and here are the known issues that will be fixed in version V1.1 or V2 depending on how much changes are needed after the full testing of V1 goes.
+The RAM interface also contains a V1 QSPI routing error, meaning the memory would require extensive rework even if the component were installed. This will therefore be corrected directly in the next PCB revision.
-### Bad selection of Rp2350 ports
+The SD card interface has a similar SPI pin-assignment issue to the W5500. Unlike the QSPI RAM issue, this can potentially be worked around using PIO SPI, as demonstrated successfully with the Ethernet interface. The SD card hardware itself was not available on the assembled V1 boards, however, so this path has not yet been validated.
-That is a pretty embarassing issue but it is not fatal. I put a bit too much faith into the internal GPIO MUX of the Rp2350 and did not respect the rules about SPI pin selection.
+### Still under evaluation
-First of all, all pins of a SPI bus need to be connected to the same SPI port, but there only are a few pins that are actually connected to a SPI port and even then not all of these pins can be used for everything. You cannot put MOSI or SCLK on any pin of the SPI port.
+The remaining work on V1 is mostly characterization rather than basic bring-up:
-Also an other issue, QSPI cannot be rerouted to any pin. The QSPI bus is only available from the QSPI specified pins which is something I missed unfortunately for the external RAM.
+- Determining the practical maximum Ethernet acquisition bandwidth using the current PIO SPI implementation
 - Quantifying analog-channel noise and signal integrity
 - Characterizing channel-to-channel consistency
 - Performing longer-duration reliability testing
-The RAM needs to be totally rerouted, 5/6 pins are wrong and need to be changed :
+Initial analog results are promising, but a more controlled measurement setup will be used before publishing quantitative results.
-```
+## Known V1 Issues
-RAM_QSD3 not to GPIO 16 but to QSPI_SD3
+
-RAM_QSD2 not to GPIO 17 but to QSPI_SD2
+V1 successfully validated the main system architecture, but bring-up also identified several routing and connector issues that will be corrected in the next revision.
-RAM_QSD1 not to GPIO 18 but to QSPI_SD1
+
-RAM_QSD0 not to GPIO 19 but to QSPI_SD0
+### RP2350 Peripheral Pin Assignment
-RAM_QSCLK not to GPIO 20 but to QSPI_SCLK
+
 The main routing issue in V1 comes from the RP2350 peripheral pin-selection constraints.
 During the original schematic and PCB design I relied too heavily on the flexibility of the RP2350 GPIO mux. Although many peripherals can be mapped to several GPIOs, SPI signals still need to follow the valid peripheral pin functions defined for each GPIO.
 This affected the W5500, SD card, and external QSPI RAM interfaces.
 The W5500 connection should be changed as follows:
 ```text
 ETH_CS   GPIO28 -> GPIO29
 ETH_SCLK GPIO29 -> GPIO30
 ETH_MISO GPIO30 -> GPIO28
 ```
-This is extremely embarassing as the pins are even labeled, I should have seen this before sending the files to production.
+On V1 this is handled in firmware using a PIO-based SPI implementation. This has been sufficient to continuously stream all 12 channels at 44.1 kHz / 16 bits, although at a lower SPI clock than would be possible with the native hardware peripheral.
-The W5500 connection needs to be rerouted as such :
+The SD card interface has the same general problem and will also be rerouted in the next revision.
-```
+### External RAM QSPI Routing
-ETH_CS GPIO28 to GPIO29
+
-ETH_SCLK GPIO29 to GPIO30
+The external RAM has a more significant routing problem.
-ETH_MISO GPIO30 to GPIO28
+
 Unlike standard SPI peripherals, the RP2350 QSPI interface cannot simply be mapped to arbitrary GPIO pins. The external memory needs to use the dedicated QSPI signals.
 The V1 connections therefore need to be changed as follows:
 ```text
 RAM_QSD3  GPIO16 -> QSPI_SD3
 RAM_QSD2  GPIO17 -> QSPI_SD2
 RAM_QSD1  GPIO18 -> QSPI_SD1
 RAM_QSD0  GPIO19 -> QSPI_SD0
 RAM_QSCLK GPIO20 -> QSPI_SCLK
 ```
-And for the SD card it's just completely wrong.
+Because five of the six main signals would require modification, the RAM interface was not considered worth extensively reworking on the V1 prototype.
-Thankfully these issues do not prevent testing as the PIO blocks can be used to create homemade SPI with custom pins, but performances will not be as the same level as they would have been with native SPI. That is why on the first batch, the RAM was not even soldered as it was not very useful to use even with PIO in my use case.
+This will be corrected directly in the next PCB revision.
-### Wrong micro USB pinout
+Interestingly, the current continuous Ethernet tests have also demonstrated that the external RAM is not required to sustain the present 12-channel 44.1 kHz / 16-bit streaming workload. It remains useful for additional buffering, standalone acquisition modes, and future higher-bandwidth configurations.
-This one looks stupid too but actually is not that ridiculous. It could have been avoided but it is not completely stupid.
+### Micro-USB Preamp Pinout
-The préamp that is supposed to be plugged into the cacao board is a custom solution that only uses the micro usb port and not protocol or guidelines. 
+The analog inputs use Micro-USB connectors purely as compact keyed connectors. They do not follow the USB electrical standard and are connected to a custom external preamplifier.
-During the design, I put 5V on the VBUS pin and GND on the GND pin. How foolish of me to not check that the designers of the AMP might have wired it completely differently putting 5V on the GND pin and GND on pin 4...
+During the original design I assigned the connector pins according to the conventional Micro-USB power arrangement, with 5 V on VBUS and ground on the normal GND pin.
-So all 12 channels actually are not powering the pre amp and are getting a signal that is waaaay too weak to be used.
+The existing preamplifier hardware uses a different custom pinout:
-A test was done by removing one port and wiring a new port with botch wire in the right order and then it worked perfectly.
+```text
-
+uUSB Pin 1 VBUS -> GND
-So for a new version you would have to make these changes :
+uUSB Pin 4 NC   -> GND
-
+uUSB Pin 5 GND  -> 5V
 ```
 uUsb Pin 1 VBUS -> GND
 uUSB Pin 4 NC -> GND (the actual GND used by the preamp)
 uUSB Pin 5 GND -> 5V
 ```
-It took longer that I want to admit to diagnose this as the signal was not truely 0. I was just getting a very weak signal but tapping the mic still gave some signal. And of course the preamp has no power on LED or anything.
+As a result, the V1 board does not correctly power the intended preamplifier when it is connected directly.
-But for now it looks like the only issues of V1 are pin assignement and that with those sorted the all system should work perfectly and with much better performance.
+This issue was diagnosed during analog bring-up. Because the microphone and preamplifier combination could still produce a very small signal even without the expected supply arrangement, the failure initially appeared as an unexpectedly low analog amplitude rather than a completely inactive channel.
 One connector was removed and rewired using bodge wires to reproduce the preamplifier's actual pinout. With this modification, the complete analog path operated correctly and produced the expected signal level.
 The remaining channels can still be observed acquiring signals with the unmodified connector arrangement, which allowed the complete 12-channel digital acquisition and Ethernet pipeline to be validated. However, the connector pinout will be corrected in the next PCB revision before proper analog characterization of all channels.
 ## Next Revision
 The next PCB revision will primarily focus on changes identified during V1 bring-up rather than a redesign of the architecture:
 - Correct W5500 hardware SPI routing
 - Correct SD card SPI routing
 - Move the external RAM to the dedicated RP2350 QSPI pins
 - Correct the Micro-USB pinout for the existing preamplifier hardware
 - Complete analog performance characterization
 - Evaluate whether architectural changes such as the W6300 are worthwhile
 The important result from V1 is that the core architecture has been validated: twelve synchronized analog channels can be acquired simultaneously by the RP2350 and continuously transmitted over Ethernet at 44.1 kHz / 16 bits per channel on a compact four-layer board.
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