# Cacao - Multi-Channel Signal Acquisition Board

Cacao is a compact 12-channel audio-frequency signal-acquisition board built around the RP2350. It explores how modern, accessible components can consolidate multi-channel acquisition, buffering, storage, and Ethernet communication onto a single 80 x 50 mm PCB.

![CACAO Board](figures/Assembled.jpeg)
![Cacao PCB - 3D render](figures/Recto.png)
![Cacao PCB - 3D render](figures/Verso.png)

The assembled board shown above had just come out of the reflow oven. Some visible solder bridges were cleaned up before the first bring-up.

## Overview

Cacao was developed independently as a proof of concept alongside an industrial R&D internship. The project acts as a technical calling card: a complete architecture, schematic, firmware stack, and dense PCB layout intended to demonstrate what can be achieved with a modern microcontroller and cost-effective audio-conversion hardware.

Twelve differential audio inputs are digitized by three TLV320ADC5140 ADCs synchronized to the same clock. The RP2350 acquires the resulting streams and can transmit them over a local network through a W5500 100BASE-TX Ethernet controller.

The current firmware has successfully demonstrated continuous simultaneous acquisition of all 12 channels at 44.1 kHz with 16-bit samples, streamed over Ethernet without requiring intermediate RAM buffering.

## Key Features

- RP2350 in the 80-pin package with internal flash
- 12 differential audio-input channels
- Three TLV320ADC5140 four-channel ADCs synchronized by a 2.5 ppm clock
- Simultaneous 12-channel acquisition at 44.1 kHz / 16 bits per sample
- W5500-based 100BASE-TX Ethernet output
- Continuous network streaming of all 12 channels
- 8 MB external RAM provisioned for acquisition buffering
- MicroSD storage interface for standalone data capture
- USB-C 5 V power input
- 3.3 V buck supply for the digital electronics
- Separate low-noise 3.3 V analog rail using an LP5907MFX-3.3/NOPB LDO
- Four-layer, 80 x 50 mm PCB with more than 200 components
- Components on both sides, with most passive components placed on the back

The Micro-USB connectors are used as compact keyed connectors for the differential analog channels and their 5 V amplifier supply. They are **not USB data ports**.

## Engineering Focus

The principal layout challenge was integrating 12 analog channels, three synchronized ADCs, local buffering, storage, Ethernet, and the required power architecture within an 80 x 50 mm footprint.

Particular attention was given to separating the low-noise analog supplies from the general digital rail, maintaining clean reference and return paths, and fitting a large number of passive components without increasing the board area.

The firmware also represents an important part of the project. The RP2350 has to receive multiple synchronized ADC data streams while simultaneously moving the acquired samples toward the Ethernet interface with minimal CPU and memory overhead.

Because of a V1 SPI pin-assignment issue, the W5500 currently runs through an RP2350 PIO implementation rather than the native SPI peripheral. Despite the reduced SPI bandwidth, the system can continuously acquire and transmit all 12 channels at 44.1 kHz / 16 bits over the local network.

This is not necessarily the absolute throughput limit of the architecture, but it is close to the useful range expected from the current PIO SPI implementation. A future revision will move the Ethernet interface to correctly assigned hardware SPI pins, providing additional bandwidth and reducing the amount of firmware required for the interface.

An alternative future configuration could also replace the W5500 and external RAM with a W6300 connected through QSPI, reducing the number of separate devices while retaining high-speed Ethernet communication.

## Assembly

The V1 PCBs were manufactured by Aisler. This was my first time using their service and the manufacturing quality was very good.

The PCBs arrived unassembled and I assembled three prototypes at school. The school has small manually controlled pick-and-place machines, which significantly speed up component placement compared with assembling the entire board using tweezers.

![CACAO Board](figures/Bare_PCB.jpeg)

![CACAO Board](figures/Compare.png)

The image above shows a bare Cacao PCB and a fully assembled board next to the existing acquisition hardware it was designed to compare against.

The other boards are blurred because they are property of the company where I worked. The comparison is nevertheless useful for showing the amount of functionality Cacao integrates onto a single board.

## Project Status

V1.0 has been manufactured, assembled, and brought up successfully.

The main architecture is operational:

- All power rails are working correctly
- The RP2350 can be programmed through both USB and SWD
- Ethernet communication through the W5500 is operational
- The W5500 is currently driven using PIO SPI because of the V1 GPIO assignment
- All three TLV320ADC5140 ADCs are operational and communicating correctly with the RP2350
- All 12 analog channels are being sampled
- All 12 channels have been acquired simultaneously at 44.1 kHz / 16 bits per sample
- The complete 12-channel stream has been transmitted continuously over the local Ethernet network
- The streaming test does not rely on the external RAM as an intermediate acquisition buffer
- A corrected Micro-USB input has been tested with the intended external preamplifier and produces the expected signal level

The continuous Ethernet test indicates that the RP2350, ADC acquisition path, PIO SPI implementation, W5500, and network firmware can sustain the current target acquisition rate without accumulating an acquisition backlog.

### Not tested on V1

Two interfaces have not yet been functionally tested:

- External RAM
- MicroSD storage

Part of the BOM could not be delivered before assembly, so the required components were not available for the first prototype batch.

The RAM interface also contains a V1 QSPI routing error, meaning the memory would require extensive rework even if the component were installed. This will therefore be corrected directly in the next PCB revision.

The SD card interface has a similar SPI pin-assignment issue to the W5500. Unlike the QSPI RAM issue, this can potentially be worked around using PIO SPI, as demonstrated successfully with the Ethernet interface. The SD card hardware itself was not available on the assembled V1 boards, however, so this path has not yet been validated.

### Still under evaluation

The remaining work on V1 is mostly characterization rather than basic bring-up:

- Determining the practical maximum Ethernet acquisition bandwidth using the current PIO SPI implementation
- Quantifying analog-channel noise and signal integrity
- Characterizing channel-to-channel consistency
- Performing longer-duration reliability testing

Initial analog results are promising, but a more controlled measurement setup will be used before publishing quantitative results.

## Known V1 Issues

V1 successfully validated the main system architecture, but bring-up also identified several routing and connector issues that will be corrected in the next revision.

### RP2350 Peripheral Pin Assignment

The main routing issue in V1 comes from the RP2350 peripheral pin-selection constraints.

During the original schematic and PCB design I relied too heavily on the flexibility of the RP2350 GPIO mux. Although many peripherals can be mapped to several GPIOs, SPI signals still need to follow the valid peripheral pin functions defined for each GPIO.

This affected the W5500, SD card, and external QSPI RAM interfaces.

The W5500 connection should be changed as follows:

```text
ETH_CS   GPIO28 -> GPIO29
ETH_SCLK GPIO29 -> GPIO30
ETH_MISO GPIO30 -> GPIO28
```

On V1 this is handled in firmware using a PIO-based SPI implementation. This has been sufficient to continuously stream all 12 channels at 44.1 kHz / 16 bits, although at a lower SPI clock than would be possible with the native hardware peripheral.

The SD card interface has the same general problem and will also be rerouted in the next revision.

### External RAM QSPI Routing

The external RAM has a more significant routing problem.

Unlike standard SPI peripherals, the RP2350 QSPI interface cannot simply be mapped to arbitrary GPIO pins. The external memory needs to use the dedicated QSPI signals.

The V1 connections therefore need to be changed as follows:

```text
RAM_QSD3  GPIO16 -> QSPI_SD3
RAM_QSD2  GPIO17 -> QSPI_SD2
RAM_QSD1  GPIO18 -> QSPI_SD1
RAM_QSD0  GPIO19 -> QSPI_SD0
RAM_QSCLK GPIO20 -> QSPI_SCLK
```

Because five of the six main signals would require modification, the RAM interface was not considered worth extensively reworking on the V1 prototype.

This will be corrected directly in the next PCB revision.

Interestingly, the current continuous Ethernet tests have also demonstrated that the external RAM is not required to sustain the present 12-channel 44.1 kHz / 16-bit streaming workload. It remains useful for additional buffering, standalone acquisition modes, and future higher-bandwidth configurations.

### Micro-USB Preamp Pinout

The analog inputs use Micro-USB connectors purely as compact keyed connectors. They do not follow the USB electrical standard and are connected to a custom external preamplifier.

During the original design I assigned the connector pins according to the conventional Micro-USB power arrangement, with 5 V on VBUS and ground on the normal GND pin.

The existing preamplifier hardware uses a different custom pinout:

```text
uUSB Pin 1 VBUS -> GND
uUSB Pin 4 NC   -> GND
uUSB Pin 5 GND  -> 5V
```

As a result, the V1 board does not correctly power the intended preamplifier when it is connected directly.

This issue was diagnosed during analog bring-up. Because the microphone and preamplifier combination could still produce a very small signal even without the expected supply arrangement, the failure initially appeared as an unexpectedly low analog amplitude rather than a completely inactive channel.

One connector was removed and rewired using bodge wires to reproduce the preamplifier's actual pinout. With this modification, the complete analog path operated correctly and produced the expected signal level.

The remaining channels can still be observed acquiring signals with the unmodified connector arrangement, which allowed the complete 12-channel digital acquisition and Ethernet pipeline to be validated. However, the connector pinout will be corrected in the next PCB revision before proper analog characterization of all channels.

## Next Revision

The next PCB revision will primarily focus on changes identified during V1 bring-up rather than a redesign of the architecture:

- Correct W5500 hardware SPI routing
- Correct SD card SPI routing
- Move the external RAM to the dedicated RP2350 QSPI pins
- Correct the Micro-USB pinout for the existing preamplifier hardware
- Complete analog performance characterization
- Evaluate whether architectural changes such as the W6300 are worthwhile

The important result from V1 is that the core architecture has been validated: twelve synchronized analog channels can be acquired simultaneously by the RP2350 and continuously transmitted over Ethernet at 44.1 kHz / 16 bits per channel on a compact four-layer board.